| Abstract: not available |
| Abstract: Detailed digital simulation studies were undertaken to identify the most critical electrical stresses for each arrester application in a dc station under overvoltage conditions. The critical contingencies identified in the application guide prepared by CIGRE WG 33/14-05 were used as a basis for evaluating arrester stresses caused by faults and converter malfunction. The point-on-wave application of the fault and instant of fault clearance were found to have a significant effect on valve and ac bus arrester stresses. It was also established that the interdependence of arresters in the series-connected arrangement in a dc station has a significant impact on the highest stresses that can be imposed on the arresters during faults. The results of the comprehensive simulation provide a useful contribution on the application of the CIGRE guidelines to a given system and will assist in developing arrester test methods representative of service conditions. The procedure used will provide guidance on determining arrester discharge capacity requirements. |
| Abstract: not available |
| Abstract: not available |
| Abstract: A static var compensator (SVC) model based on state variable techniques is presented. This model is capable of being interfaced to a parent (or host) electromagnetic transients program, and a stable method of interfacing to the EMTDC program, in particular, is described. The model is primarily that of a thyristor controlled reactor (TCR) and a thyristor switched capacitor (TSC). Capacitor switchings within the TSC have been handled in a novel way to simplify storage and computation time requirements. During thyristor switching, the child SVC model is capable of using a smaller time step than the one used by the parent electromagnetic transients program; after the switching, the SVC model is capable of reverting back to a (larger) time step compatible with the one used by the parent program. Other features that are considered include the modeling of a phase-locked-loop based valve firing system. The paper ends with the discussion of an application of this model in the simulation of a SVC controlling the ac voltage at the inverter bus of a back-to-back HVdc tie. |
| Abstract: A description of how accurate system modelling of a dc system with an electromagnetic transient simulation program can be used to study and correct interbipole oscillations between converters connected into a parallel multiterminal system is given. This paper shows how to decide on the detail of modelling that is required, and demonstrates that it is often not enough to use prepackaged, generic HVDC control models, supplies with these programs. the detail of control models that are used in the electromagnetic simulation programs are shown to have a significant impact, in some cases, on the simulation results. In particular, a case of six hertz oscillations, in the dc currents of two converters on the Nelson River System, is accurately simulated, and it is shown that control modifications suggested by the simulation actually do eliminate the interbipole oscillations. |
| Abstract: HVdc converters connected into weak ac systems require effective application of voltage control devices to ensure satisfactory voltage control and recovery following disturbances. Both an MOV arrangement and a series capacitor were found to be potentially very cost effective solutions in investigations using digital simulation. However, although the series capacitor performed well in controlling temporary overvoltage following HVdc load rejection, satisfactory recovery from faults was difficult to obtain. This paper presents a follow-up study which uses a state-of-the-art analogue simulator to further investigate the performance of the MOV and series capacitor arrangements, especially the fault recovery performance of the latter. |
| Abstract: not available |
